To better understand the advance in the art that the present invention provides a prior art floating buck converter circuit 100 will first be described. As shown in FIG. 1, prior art floating buck converter circuit 100 comprises the following elements: diode 110, capacitor 120, load 130, inductor 140, transistor 150 (here shown as a field effect transistor (FET) designated “MAIN FET M0”), resistor RSNS, pulse width modulation (PWM) control unit 160 and gate driver 170. The diode 110, capacitor 120 and the load 130 are coupled in parallel with a first end of each element coupled to the input voltage VIN. The load 130 shown in FIG. 1 comprises a plurality of serially connected light emitting diodes (LEDs). The output current through the load 130 is designated IOUT.
A first end of inductor 140 is coupled to the second end of diode 110 and to the drain of transistor 150. A second end of inductor 140 is coupled to the second end of load 130 and the second end of capacitor 120. The current through inductor 140 is referred to as the inductor current and is designated with the letters IL.
The source of transistor 150 is coupled to a first end of resistor RSNS. The second end of resistor RSNS is coupled to ground. The current through the transistor 150 is referred to as the transistor current and is designated by the letters IFET. A first end of a voltage signal line 180 is coupled to node between transistor 150 and resistor RSNS. The value of voltage at the node is designated with the letters VSNS. The second end of the voltage-signal line 180 is provided to an input of the pulse width modulation (PWM) control unit 160. An output of the pulse width modulation (PWM) control unit 160 is provided to gate driver 170. The output of gate driver 170 is connected to the gate of transistor 150. Control signals from the pulse width modulation (PWM) control unit 160 are provided through gate driver 170 to the gate of transistor 150 to control the transistor current and the output current IOUT. The pulse width modulation (PWM) control unit 160 monitors the value of the voltage signal VSNS on voltage signal line 180 and adjusts the value of the control signals to gate driver 170 based on the average value of the VSNS voltage.
FIG. 2 illustrates a schematic circuit diagram 200 of the prior art floating buck converter circuit 100 shown in FIG. 1 showing the pulse width modulation (PWM) control unit 160 in more detail. The second end of the voltage signal line 180 is provided to an input of a leading edge blanking unit 210. The operation of the leading edge blanking unit 210 removes any voltage “spike” that may be present at the leading edge of the VSNS voltage signal.
The output of the leading edge blanking unit 210 is provided to a non-inverting input of a comparator unit 220. A reference voltage VREF is provided to the inverting input of comparator unit 220. The output of comparator unit 220 is provided to the pulse width modulation (PWM) control logic circuit 230. As shown in FIG. 2, the PWM control logic circuit 230 comprises a first edge pulse generator unit 240, a second edge pulse generator unit 250, a first NOR gate 260, a second NOR gate 270, and a third NOR gate 280.
As shown in FIG. 2, an input line 290 provides a pulse signal to the first edge pulse generator unit 240 and to the second edge pulse generator 250. The first edge pulse generator unit 240 generates a first control signal pulse and provides the first control signal pulse to an A1 input of the third NOR gate 280. The second edge pulse generator unit 250 generates a second control signal pulse and provides the second control signal pulse to an A1 input of the first NOR gate 260.
The comparator 220 generates a third control signal by comparing the reference voltage VREF to the VSNS voltage signal on voltage signal line 180. The comparator 220 provides the third control signal to an A2 input of the second NOR gate 270. The output of first NOR gate 260 and the output of second NOR gate 270 are cross-coupled. That is, the output of the first NOR gate 260 is provided to the A1 input of the second NOR gate 270. The output of the second NOR gate 270 is provided to the A2 input of the first NOR gate 260. The output of the first NOR gate 260 is also provided to the A2 input of the third NOR gate 280. The output of the third NOR gate 280 is provided to the gate driver 170.
The general principles of operation of the prior art floating buck converter circuit 100 shown in FIG. 1 (and the circuit 200 shown in FIG. 2) are well known in the art. Prior art floating buck converter circuits operate by sensing the sloped rise portion of the inductor ripple current. However, the choice of a particular value for inductor 140 will alter the average output current.
Consider, for example, the two waveforms of inductor current 300 shown in FIG. 3. The first waveform 310 for a first inductor illustrates a first inductor ripple current in a prior art floating buck converter circuit. The second waveform 320 for a second inductor illustrates a second inductor ripple current in the same prior art floating buck converter circuit.
The value of peak current is the same for both the first waveform 310 and the second waveform 320. However, the average current for the first waveform 310 (“Average Current 1”) is greater than the average current for the second waveform 320 (“Average Current 2”). The prior art method of sensing the peak value of current to regulate the peak inductor current does not determine a true average output current value. This leads to less precision in the average output current regulation. Therefore it would be desirable to have an apparatus and method that could determine a true value of the average output current and utilize the true value to provide a true average output current regulation.
FIG. 4 illustrates generic waveforms of a prior art floating buck converter circuit. FIG. 4(a) shows the inductor current IL as a function of time. The inductor current ripple is designated with the letters Irip. The average value of the inductor current IL is equal to the direct current (DC) output current IOUT. FIG. 4(b) shows the field effect transistor current IFET as a function of time. The mid-level value of the IFET current during the sloped rise of the IFET current is equal to the direct current (DC) output current IOUT. As shown in FIG. 4(b), the increase in the IFET current during its sloped rise is equal to the inductor current ripple Irip. When the IFET current has increased by a value of one half Irip (“Irip/2”) from the beginning of the sloped increase in current then the IFET current has reached a value of the direct current (DC) output current IOUT.
FIG. 4(c) shows the value of the VSNS voltage signal as a function of time. The mid-level value of the VSNS voltage signal during the sloped rise of the VSNS voltage is equal to the product of the direct current (DC) output current IOUT and the resistance RSNS. Comparing FIG. 4(b) and FIG. 4(c) leads to the relationship shown in FIG. 4(d). The mid-level of the sloped rise of the VSNS voltage (that originated from the inductor current ripple Irip) is equal to the product of the direct current (DC) output current IOUT and the resistance RSNS.
As shown in FIG. 4(d), the increase in the VSNS voltage during its sloped rise is equal to the product of the inductor current ripple Irip and the resistance RSNS. When the VSNS voltage has increased by a value of one half Irip (“Irip/2”) times the resistance RSNS from the beginning of the sloped increase in voltage then the VSNS voltage has reached a value of the direct current (DC) output current IOUT times the resistance RSNS.
There is a need in the art for a system and method that is capable of precisely regulating the direct current (DC) output current of a floating buck converter circuit. There is also a need in the art for a system and method that is capable of determining a true value of the average output current and utilizing the true value to provide a true average output current regulation in a floating buck converter circuit.
One prior art approach to controlling a floating buck converter circuit is set forth in a paper entitled Dynamic Effects of Inductor Current Ripple in Average Current Mode Control by T. Suntio, J. Lempinen et al. published in the 32nd Annual IEEE Power Electronics Specialists Conference, 17-21 Jun. 2001, Volume 3, pp. 1259-1264. Another prior art approach to controlling a floating buck converter circuit is set forth in a paper entitled DC-to-DC Buck Converters with Novel Current Mode Control by Z. Yang and P. C. Sen published in the 30th Annual IEEE Power Electronics Specialists Conference, 27 Jun.-1 Jul. 1999, Volume 2, pp. 1158-1164.
The assignee of the present patent application also has a related patent application entitled Versatile System for High-Power Switching Controller in Low-Power Semiconductor Technology filed on Nov. 2, 2005 with patent application Ser. No. 11/265,783.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
The term “controller” means any device, system, or part thereof that controls at least one operation. A controller may be implemented in hardware, software, firmware, or combination thereof. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.